BrainChip Unveils Processor IP Core For On-Device Generative AI

KUALA LUMPUR, Oct 15 (Bernama) -- BrainChip Holdings Ltd has unveiled BrainChip Sequora Core IP, a processor intellectual property (IP) core that runs generative artificial intelligence (AI), including large language models (LLMs), directly on battery-powered edge devices.

Sequora builds on BrainChip’s Akida platform. Its efficiency comes from a state-space design that keeps memory use fixed regardless of how long the data stream or conversation runs, allowing it to scale from models of a few million parameters up to three billion.

Devices that once could only recognise a signal can now understand, explain and respond, the company said in a statement.

“Customers are not asking for just a signal classifier or a language model. They want both, in the same product, on the same battery. Akida and Sequora together deliver exactly that,” said BrainChip chief executive officer, Sean Hehir.

According to BrainChip, Sequora removes the memory and power bottleneck that has kept generative AI out of battery-powered devices such as earbuds and sensor nodes.

Paired with Akida, it brings two workloads together. Akida processes streaming sensor data such as vibration, audio, radar, raw radio-frequency (RF) IQ data and biological signals, while Sequora runs generative and sequential AI, including on-device LLMs, voice-to-voice interaction and AI agents.

The company said target markets include consumer voice and wearables, aerospace and defence, automotive and industrial radar, industrial Internet of Things (IoT), and medical devices, all of which need conventional and generative AI in the same product.

Because Sequora runs AI without sending data off the device, it also keeps data and AI models on the device while minimising size, weight and power, BrainChip said.

Sequora is available now as licensable semiconductor IP, which customers integrate into their own system-on-chip (SoC) and manufacture at the foundry and process node of their choice. It is delivered as process-portable, fully synthesisable register-transfer level (RTL) code, with verification IP, a testbench, synthesis scripts and timing constraints.

-- BERNAMA